1. Field of the Invention
The present invention relates to a signal processing apparatus for applying various kinds of processing to digital data.
2. Description of the Prior Art
In conventional cameras using CCD (Charge Coupled Device) image sensors, the output of the image sensor is subjected to gamma correction, edge correction and so on. With a color camera, particularly, the image sensor output is also subjected to white balance regulation, high-bright pseudo signal suppression and so on. Thus, the color camera will have many items to be processed. In such a signal processing circuit, the setting of signal processing condition is easier and the signals are less degraded. Therefore, the signal processing mode tends to be shifted from the analog mode to the digital mode.
FIG. 1 is a block diagram of a camera having a digital processing mode.
CCD image sensor 1 has a plurality of light receiving pixels disposed in a matrix. The light receiving pixels accumulate information charges produced in response to the incident light. CCD driver 2 supplies a multi-phase transfer clock to the image sensor 1 and causes the respective light receiving pixels to transfer the charges accumulated therein for forming an image signal Y.sub.1(t). An analog signal processing unit 3 executes sample and hold, automatic gain control (AGC), and other processes relative to the image signal Y.sub.1(t), to form an output image signal Y.sub.2(t). The image signal Y.sub.2(t) is then converted into digital data by an A/D converting circuit 4 to generate image data D.sub.1(t) which is in turn inputted into a digital signal processing unit 5. The digital signal processing unit 5 applies gamma correction and reference level clamp and, particularly with the color camera, also executes white balance regulation, high-bright pseudo signal suppression and so on, to generate image data D.sub.2(t). The image data D.sub.2(t) is then converted into analog values, to generate an image output signal Y.sub.3(t), by a D/A converter 6.
The analog and digital signal processing units 3, 5 respectively receive control commands for setting the condition of signal processing. For example, the analog signal processing unit 3 may receive, as a voltage value, a reference voltage used to perform the sample and hold of the image signal Y.sub.1(t) or a reference voltage used to carry out the automatic gain control. On the other hand, the digital signal processing unit 5 may receive the information of adjustment for gamma correction coefficient and white balance regulation in the form of digital data that comprises an appropriate number of bits.
If the digital signal processing unit 5 receiving the control command in the form of digital data is to be composed of an integrated circuit, it is connected to a serial register 7, as shown in FIG. 2. First of all, a plurality of setting data are sequentially inputted and stored in the serial register 7 to set the operational conditions of the digital signal processing unit 5. The serial register 7 then provides the setting data to the setting inputs S.sub.1 -S.sub.n of the digital signal processing unit 5 at the same time. Thus, even if only a single input pin is used to input the setting data, a plurality of control data can be supplied to the digital signal processing unit 5 through the serial register 7.
Thus, the total number of bits in all the setting data required by the digital signal processing unit 5 will be continuously inputted and stored in the serial register 7. Even if it is desired to change only a part of the setting data, therefore, all the setting data must be newly received by the serial register 7. This necessarily requires peripheral equipment for inputting the setting data into the serial register 7, resulting in an increase in the manufacturing cost. As color image signals require more setting conditions, the setting data to be written into the serial register 7 is also increased. This raises a problem in that the setting data are to be rewritten in the serial register 7. In this regend, the serial register 7 may be a shift register for transferring the data in synchronism with the serial transfer clock of the setting data.